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datasheet femtoclock ? ng crystal-to-lvcmos/ lvttl clock synthesizer ICS840N011I ics840n011bgi revision a august 16, 2013 1 ?2013 integrated device technology, inc. general description the ICS840N011I is an lvcmos/lvttl clock synthesizer designed for fibre channel applications. the device generates a 106.25mhz clock signal from a 26.5625mhz crystal or a 100mhz clock signal from a 25mhz crystal with excellent phase jitter performance. the device uses idt?s fourth generation femtoclock ? ng technology for an optimum of high clock frequency, low phase noise performance and low power consumption and high power supply noise rejection.the device supports 2.5v or 3.3v voltage supply and is packaged in a small, lead-free (rohs 6) 8-lead tssop package. the extended temperature range supports wireless infrastructure, telecommunication and networking end equipment requirements. frequency table function table note: oe is an asynchronous control. features ? fourth generation femtoclock ? ng technology ? 106.25mhz output clock synthesized from a 26.5625mhz fundamental mode crystal ? one 2.5v or 3.3v lvcmos/lvttl clock output ? crystal interface designed for a 12pf parallel resonant crystal ? rms phase jitter @ 100mhz, using a 25mhz crystal (637khz - 10mhz): 0.185ps (maximum) ? lvcmos/lvttl interface level for the output enable input ? full 2.5v or 3.3v supply voltage ? lead-free (rohs 6) packaging ? -40c to 85c ambient operating temperature f xtal (mhz) output frequency (mhz) 25 100 26.5625 106.25 30.72 122.88 31.25 125 input output enable oe 0 output q is disabled in high-impedance state 1 (default) output q is enabled. block diagram pin assignment ICS840N011I 8-lead tssop 4.40mm x 3.0mm x 0.925mm package body g package top view 8 vdd 7q 6 gnd 5 dnu vdda 1 oe 2 xtal_out 3 xtal_in 4 osc xtal_in xtal_out oe 24 pfd & lpf femtoclock ? ng vco 588-765mhz 6 pullup q
ics840n011bgi revision a august 16, 2013 2 ?2013 integrated device technology, inc. ICS840N011I data sheet femtoclock ? ng crystal-to-lvcmos/lvttl clock synthesizer pin descriptions and characteristics table 1. pin descriptions note: pullup refers to an internal input resistor. see table 2, pin characteristics, for typical values. table 2. pin characteristics number name type description 1v dda power analog power supply. 2 oe input pullup output enable pin. lvcmos interface levels. 3, 4 xtal_out, xtal_in input crystal oscillator interface. xtal_in is the input, xtal_out is the output. 5 dnu do not use. do not connect. 6 gnd power power supply ground. 7 q output single-ended clock output. lvcmos/lvttl interface levels. 8v dd power core supply pin. symbol parameter test conditions minimum typical maximum units c in input capacitance oe 3.5 pf c pd power dissipation capacitance v dd = 3.465v 11 pf v dd = 2.625v 9 pf r pullup input pullup resistor 51 k ? r out output impedance v dd = 3.3v 15 ? v dd =2.5v 19 ?
ics840n011bgi revision a august 16, 2013 3 ?2013 integrated device technology, inc. ICS840N011I data sheet femtoclock ? ng crystal-to-lvcmos/lvttl clock synthesizer absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operation of product at these conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc electrical characteristics table 3a. power supply dc characteristics, v dd = 3.3v5% or 2.5v5%, t a = -40c to 85c table 3b. lvcmos/lvttl dc characteristics, v dd = 3.3v5% or 2.5v5%, t a = -40c to 85c note 1: output terminated with 50 ? to v dd / 2. see parameter measurement information section, lvcmos output load test circuit diagrams. item rating supply voltage, v dd 3.63v inputs, v i xtal_in other inputs 0v to 2v -0.5v to v dd + 0.5v outputs, v o -0.5v to v dd + 0.5v package thermal impedance, ? ja 117c/w (0 mps) storage temperature, t stg -65 ? cto150 ? c symbol parameter test conditions minimum typical maximum units v dd core supply voltage 2.375 3.3 3.465 v v dda analog supply voltage v dd ? 0.18 3.3 v dd v v dda analog supply voltage v dd ? 0.18 2.5 v dd v i dda analog supply current 18 ma i dd power supply current 67 ma symbol parameter test conditions minimum typical maximum units v ih input high voltage v dd = 3.3v 2 v dd + 0.3 v v dd = 2.5v 1.7 v dd + 0.3 v v il input low voltage v dd = 3.3v -0.3 0.8 v v dd = 2.5v -0.3 0.7 v i ih input high current oe v dd =v in = 3.465v or 2.625v 5 a i il input low current oe v dd = 3.465v 3.465v or 2.625v, v in =0v -150 a v oh output high voltage; note 1 q v dd = 3.465v 2.6 v v dd = 2.625v 1.8 v v ol output low voltage; note 1 qv dd = 3.465v or 2.625v 0.5 v
ics840n011bgi revision a august 16, 2013 4 ?2013 integrated device technology, inc. ICS840N011I data sheet femtoclock ? ng crystal-to-lvcmos/lvttl clock synthesizer table 4. crystal characteristics ac characteristics table 5. ac characteristics, v dd = 3.3v5% or 2.5v5%, t a = -40c to 85c note: characterized with 25mhz, 26.5625mhz, 30.72mhz and 31.25mhz crystals. note 1: please refer to the phase noise plots. parameter test conditions minimum typical maximum units mode of oscillation fundamental frequency 24.50 26.5625 31.88 mhz equivalent series resistance (esr) 80 ? shunt capacitance 7pf capacitive load (c l ) 12 pf symbol parameter test conditions minimum typical maximum units f out output frequency 98.00 106.25 127.52 mhz t jit(?) rms phase jitter (random); note 1 f out = 100mhz, 25mhz crystal, integration range: 637khz ? 10mhz 0.140 0.185 ps f out = 106.25mhz, 26.5625mhz crystal, integration range: 637khz ? 10mhz 0.139 0.177 ps ? n single-side band noise power f out = 106.25mhz, offset: 10hz -60.4 dbc/hz f out = 106.25mhz, offset: 100hz -87.4 dbc/hz f out = 106.25mhz, offset: 1khz -117.8 dbc/hz f out = 106.25mhz, offset: 10khz -130.7 dbc/hz f out = 106.25mhz, offset: 100khz -134.9 dbc/hz f out = 106.25mhz, offset: 1mhz -145.6 dbc/hz f out = 106.25mhz, offset: 10mhz -158.9 dbc/hz t r /t f output rise/fall time 20% to 80% 200 600 ps odc output duty cycle 48 52 %
ics840n011bgi revision a august 16, 2013 5 ?2013 integrated device technology, inc. ICS840N011I data sheet femtoclock ? ng crystal-to-lvcmos/lvttl clock synthesizer typical phase noise at 100mhz (637khz - 10mhz) typical phase noise at 106.25mhz (637khz - 10mhz) noise power (dbc/hz) offset frequency (hz) noise power (dbc/hz) offset frequency (hz)
ics840n011bgi revision a august 16, 2013 6 ?2013 integrated device technology, inc. ICS840N011I data sheet femtoclock ? ng crystal-to-lvcmos/lvttl clock synthesizer parameter measurement information 2.5v lvcmos/lvttl output load ac test circuit rms phase jitter output duty cycle/pulse width/period 3.3v lvcmos/lvttl output load ac test circuit output rise/fall time scope qx gnd 1.25v 5% -1.25v 5% 1.25v 5% v dd v dda q t period t pw t period odc = v dd 2 x 100% t pw scope qx gnd v dd 1.65v 5% -1.65v 5% v dda 1.65v 5% q 20% 80% 80% 20% t r t f
ics840n011bgi revision a august 16, 2013 7 ?2013 integrated device technology, inc. ICS840N011I data sheet femtoclock ? ng crystal-to-lvcmos/lvttl clock synthesizer applications information overdriving the xtal interface the xtal_in input can be overdriven by an lvcmos driver or by one side of a differential driver through an ac coupling capacitor. the xtal_out pin can be left floating. the amplitude of the input signal should be between 500mv and 1.8v and the slew rate should not be less than 0.2v/ns. for 3.3v lvcmos inputs, the amplitude must be reduced from full swing to at least half the swing in order to prevent signal interference with the power rail and to reduce internal noise. figure 1a shows an example of the interface diagram for a high speed 3.3v lvcmos driver. this configuration requires that the sum of the output impedance of the driver (ro) and the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the crystal input will attenuate the signal in half. this can be done in one of two ways. first, r1 and r2 in parallel should equal the transmission line impedance. for most 50 ? applications, r1 and r2 can be 100 ? . this can also be accomplished by removing r1 and changing r2 to 50 ? . the values of the resistors can be increased to reduce the loading for a slower and weaker lvcmos driver. figure 1b shows an example of the interface diagram for an lvpecl driver. this is a standard lvpecl termination with one side of the driver feeding the xtal_in input. it is recommended that all components in the schematics be placed in the layout. though some components might not be used, they can be utilized for debugging purposes. the datasheet specifications are characterized and guaranteed by using a quartz crystal as the input. figure 1a. general diagram for lvcmos driver to xtal input interface figure 1b. general diagram for lvpecl driver to xtal input interface
ics840n011bgi revision a august 16, 2013 8 ?2013 integrated device technology, inc. ICS840N011I data sheet femtoclock ? ng crystal-to-lvcmos/lvttl clock synthesizer schematic layout figure 2 shows an example ICS840N011I application schematic in which the device is operated at v dd =v dda = +3.3v. the schematic example focuses on functional connections and is intended as an example only and may not represent the exact user configuration. refer to the pin description and functional tables in the datasheet to ensure the logic control inputs are properly set. for example oe can be configured from an fpga instead of set with pull up and pull down resistors as shown. as with any high speed analog circuitry, the power supply pins are vulnerable to random noise, so to achieve optimum jitter performance isolation of the v dd pin from power supply is required. in order to achieve the best possible filtering, it is recommended that the placement of the filter components be on the device side of the pcb as close to the power pins as possible. if space is limited, the 0.1f capacitor on the v dd pin must be placed on the device side with direct return to the ground plane though vias. the remaining filter components can be on the opposite side of the pcb. power supply filter component recommendations are a general guideline to be used for reducing external noise from coupling into the devices. the filter performance is designed for a wide range of noise frequencies. this low-pass filter starts to attenuate noise at approximately 10khz. if a specific frequency noise component is known, such as switching power supplies frequencies, it is recommended that component values be adjusted and if required, additional filtering be added. additionally, good general design practices for power plane voltage stability suggests adding bulk capacitance in the local area of all devices. figure 2. ICS840N011I application schematic
ics840n011bgi revision a august 16, 2013 9 ?2013 integrated device technology, inc. ICS840N011I data sheet femtoclock ? ng crystal-to-lvcmos/lvttl clock synthesizer power considerations this section provides information on power dissipation and junction temperature for the ICS840N011I. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ICS840N011I is the sum of the core power plus the analog power plus the power dissipated in the load(s). the following is the power dissipation for v dd = 3.3v + 5% = 3.465v, which gives worst case results. ? power (core) max =v dd_max *(i dd +i dda ) = 3.465v *(67ma + 18ma) = 294.53mw ? output impedance r out current due to loading 50 ? to v dd /2 output current i out =v dd_max /[2*(50 ? +r out )] = 3.465v / [2 * (50 ? +15 ? )] = 26.7ma ? power dissipation on the r out per lvcmos output power (r out )=r out *(i out ) 2 =15 ? * (26.7ma) 2 = 10.7mw ? total power (r out ) = 10.7m w*1= 10.7mw dynamic power dissipation at 125mhz power (125mhz) = c pd * frequency * (v dd ) 2 = 11pf * 125mhz * (3.465v) 2 = 16.51mw total power (125mhz) = 16.51m w*1= 16.51mw total power dissipation ? total power = power (core) max + power (r out ) + power (125mhz) = 294.53mw + 10.7mw + 16.51mw = 321.74mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. the maximum recommended junction temperature is 125c. limiting the internal transistor junction temperature, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ? ja * pd_total + t a tj = junction temperature ? ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance q ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 117c/w per table 6 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.322w *117c/w = 122.7c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). table 6. thermal resistance ? ja for 8 lead tssop, forced convection ? ja by velocity meters per second 0 multi-layer pcb, jedec standard test boards 117c/w
ics840n011bgi revision a august 16, 2013 10 ?2013 integrated device technology, inc. ICS840N011I data sheet femtoclock ? ng crystal-to-lvcmos/lvttl clock synthesizer reliability information table 7. ? ja vs. air flow table for a 8-lead tssop transistor count the transistor count for ICS840N011I is: 24,811 package outline and package dimensions package outlin e - g suffix for 8 lead tssop table 8. package dimensions reference document: jedec publication 95, mo-153 ? ja vs. air flow meters per second 0 multi-layer pcb, jedec standard test boards 117c/w all dimensions in millimeters symbol minimum maximum n 8 a 1.20 a1 0.5 0.15 a2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 d 2.90 3.10 e 6.40 basic e1 4.30 4.50 e 0.65 basic l 0.45 0.75 ? 0 8 aaa 0.10
ics840n011bgi revision a august 16, 2013 11 ?2013 integrated device technology, inc. ICS840N011I data sheet femtoclock ? ng crystal-to-lvcmos/lvttl clock synthesizer table 9. ordering information part/order number marking package shipping packaging temperature 840n011bgilf 11bil lead-free, 8-lead tssop tube -40 ? cto85 ? c 840n011bgilft 11bil lead-free, 8-lead tssop tape & reel -40 ? cto85 ? c
ICS840N011I data sheet femtoclock ? ng crystal-to-lvcmos/lvttl clock synthesizer disclaimer integrated device technology, inc. (idt) and its subsidiaries reserve the right to modify the products and/or specif ications described herein at any time and at idt?s sole discretion. all information in this document, including descriptions of product features and performance, is subject to change without notice. performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. the information contained herein is provided without re presentation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of idt?s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the in tellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third parties. idt?s products are not intended for use in applications involving extreme environmental conditions or in life support systems o r similar devices where the failure or malfunction of an idt product can be reasonably expected to signifi- cantly affect the health or safety of users. anyone using an idt product in such a manner does so at their own risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are registered trademarks of idt. other trademarks and service marks used he rein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright 2013. all rights reserved. 6024 silver creek valley road san jose, california 95138 sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt technical support sales netcom@idt.com +480-763-2056 we?ve got your timing solution

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